FPGA Implementation of a Reduct Generation Algorithm based on Rough Set Theory

Rough Set theory, proposed by Pawlak in 1982, is a mathematical tool for classification and analysis of imprecise, uncertain, incomplete or vague information and knowledge. Using various concepts in RST, classification of objects in various classes is done by removing irrelevant and redundant data by using attribute reduction algorithm. Attribute reduction using Rough set theory is one of the key problems. Also to find minimal attributes is a NP-hard problem. Attribute reduction is a preprocessing step in data mining, pattern recognition, machine learning, etc. In this paper, we present a literature survey of various existing algorithms and comparing them on its time and space complexity. In this paper, a hardware implementation of attribute reduction algorithm for classification purpose is proposed. Functional verification of model is done and simulation results are shown.